Doherty RF PA design

  Doherty paper, level of physics

artifact

HW#12 PnR for Apple C1 PLL and RISC Core CPU

本次習題基本說明 PLL

進階說明 PLL

講義

on Apple C1 PLL

on Modern Placement Algorithms

課堂練習 

Deadline: Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#12 [your id, your name]

任選一題

 1. Use this physics model to identify a high efficiency Class F RF amplifier. ASAP7 Class-F (auto-load)

dual attractors

basin transitions

Amplifier class (harmonics in PA design)

2.（a)Build a model of Apple C1 ADPLL — 7.0 GHz (spec) with A* and NM Version, NM cross checked by MNA,  

(b) Enhance the Apple C1 PLL model with DTC by building an Optimizer with MNA-powered trajectory. share, DTC-Solver

You may refer to schematic, architecture and timing, DTC-TDC Timing (share)

Apple C1 ADPLL — 7.0 GHz  (C1 is N4P)

Head-to-head

3. Write an algorithm for Macro Routing for a RISC core CPU, starting from the baseline to Bit sliced macro

 baseline macro 32, metal layers 3, die 550 × 600 μm

add timing

add CTS

add std cells

add logistic prob of wins

Bit sliced macro 28, metal layers 9, die 690 × 750 μm

Two-stage Class-AB RF PA driver: parameter optimization GaN

 GaN, "Calibrated for 0.25 µm GaN-on-SiC RF process (Wolfspeed G2 / WIN NP25 class)" for base station

artifact (topology change, single device)

LNA Chip Physics Model, PnR

 

LNA Physics Model

artifact

LNA PnR

artifact

artifact

HW#11 RF IC Placement & Routing

  Benchmark  Two-stage Cascode Class-AB RF power amplifier targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Experiment with 30 seeds

Measure success, congestion, wirelength, overlap pairs (before/after)

Placement style 1

Placement artifact style 2

benchmark

 

Benchmark the P&R for OP 741.

Experiment with 3 seeds

Measure success, congestion, wirelength, overlap pairs (before/after), Vin length match

Placer & Router for OP 741

benchmark

HW#10 RF PA Driver Design (physics vs. closed-form)

 1. Benchmark the three designs of RF PA Drivers

2-stage RF PA driver 

Closed-form Optimizer with Load-Pull Contours 

Performance-first Thermal build  ∠Γ_3f₀ phase (deg) · open=0, -170 deg

Margin-first Thermal build ∠Γ_3f₀ phase (deg) · open=0, -170 deg

Using Cowork or Claude.ai, benchmark the three models. Experiment with 5 seeds. For each seed, optimize the circuit design using built-in A* and then NM. 

For each seed, record metrics from the cascaded optimizers: 

Compare Closed-Form vs. margin-first build vs. comprehensive model. 

-Tabulate Gain, Pout, PAE, OP1dB, S₁₁ (5 metrics × 10 seeds = 40 cells).

-Identify which metric the closed-form most over- or under-estimates.

Cross-check both thermal designs: compute junction temperature rise ΔT_j at peak Pout. Which design runs cooler? By how many °C?

-Build a 2×2 comparison table: rows = {Performance-first, Margin-first}, columns = {Fitness, min-spec-margin (dB), ΔT_j (°C), PAE @ 6dB back-off}.

Visualize all of your data

Supplemental

Margin vs. Performance builds

design choices 

Training Pipeline in Claude Cowork- OPC lithography hotspot detection code

wrap in slides