HW#14 Robot and BLV Navigation

課堂練習 

Deadline:  Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#14 [your id, your name]

 1,2 二選一

1. 參考Voronoi navigation app，製作以下場景的導航（可使用前一次作業的3d model）

task 1: make an entrance/exit. make the auto-navigation route deliberately exit through this gate (e.g., a waypoint placed just outside on the brick path) and go to central woods as destination.

task 2: set FPV (first-person view) and maintain horizontal view angle

task 3: show Voronoi Waypoints for navigation

提示：給還不熟悉Claude 的同學，如何套用既有導航系統到這個溜冰場情境(如照片)，已經會套用artifact 同學可以跳過

如何套用 https://claude.ai/share/8ac9c5a7-4944-41e7-a1af-027635b14dac

2. Implement Voronoi-based navigation for robots or BLV users

Non-Voronoi Navigation

3. Benchmark the two static vs. dynamic Voronoi-based navigation. 30 seeds.

Voronoi start-up A* + Repelling

dynamic voronoi

Follow up HW#13

 Problem 1

以下是比較不同演算法得出的繞線以及比較不同繞線的電路效能

Trace Routing Errors and Repairs router optimization （original by Ms. Wu）

A* vs Dijkstra side-by-side comparison originally by Ms. Kuo

Problem 2

suggestions

- Add a short note on how CL1 and CL2 set the load capacitance the crystal sees: CL = (CL1*CL2)/(CL1+CL2) + Cstray. With 22 pF caps this lands near the common 12 to 18 pF crystal spec once stray is included, and stating it explicitly ties your part choices to the datasheet.

pierceCalc

Consider analysis of heatmap

trace, 3d, heat map＊ heat map by me, trace route and 3D by Mr. Su

HW#13 Circuit Optimization on PCB

課堂練習 

Deadline:  Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#13 [your id, your name]

1. Optimize trace routing for the Differential Pair Circuit on PCB 

trace routing, share (artifact, more accurate schematic)

Steps

Starting from the imperfect design, complete the trace routing. Do trace routing ( 參考 share, share 2, share 3)

我是希望你們可以自行變換

無論是優化，更換演算法，UI 都可以，總之不是複製

2. 設計Crystal 石英振盪電路的PCB

 (slides) schematic

除了ＰＣＢ視覺化，我是希望可以做一下 sensitivity analysis 或是 heat map

(3, 4 任選一題來做)

3. 使用鑽孔路徑演算法進行以下PCB 鑽孔(演算法 提供參考)

PCB 1

4. 

PCB 2

甚麼是 TSP?

Traveling Salesman Problem 簡稱TSP

 (一個推銷員要拜訪所有客戶城市，每個城市只能拜訪一次，最後要回到出發城市，請為他/她計算最短的拜訪路徑)

TSP在工業界有重要應用，包括物流（UPS/Amazon配送路線優化）、製造業（電路板鑽孔、機器人組裝路徑）、電信（網路路由、線路安裝）和能源（電網維護、管線檢查）。凡是需要造訪多個地點同時最小化成本、時間或距離的場合都適用。現代變體能處理容量限制、時間窗口等實際約束。企業使用OR-Tools、Gurobi等專業軟體解決這些問題，透過優化倉儲揀貨、切割模式、3D列印路徑和車隊管理等作業，往往能節省數百萬成本。

(樸素) Visualize TSP (Traveling Salesman Problem) by A* search 使其可以改變網路節點個數

(美學) 視覺化 A* for Traveling Salesman Problem 使其可以改變網路節點個數

Search for a Class-F RF PA. (Follow up HW#12)

 我用 Claude cowork 找了滿足條件的 Class-F

artifact

fitness function disfavors class-F (HD3 floor constraint wants it be class-AB), relaxed during search

class-F note: the two solutions are within the same basin

s11, s22 repair, dashboard

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Doherty RF PA design

  Doherty paper, level of physics

artifact

HW#12 PnR for Apple C1 PLL and RISC Core CPU

本次習題基本說明 PLL

進階說明 PLL

講義

on Apple C1 PLL

on Modern Placement Algorithms

課堂練習 

Deadline: Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#12 [your id, your name]

任選一題

 1. Use this physics model to identify a high efficiency Class F RF amplifier. ASAP7 Class-F (auto-load)

dual attractors

basin transitions

Amplifier class (harmonics in PA design)

2.（a)Build a model of Apple C1 ADPLL — 7.0 GHz (spec) with A* and NM Version, NM cross checked by MNA,  

(b) Enhance the Apple C1 PLL model with DTC by building an Optimizer with MNA-powered trajectory. share, DTC-Solver

You may refer to schematic, architecture and timing, DTC-TDC Timing (share)

Apple C1 ADPLL — 7.0 GHz  (C1 is N4P)

Head-to-head

3. Write an algorithm for Macro Routing for a RISC core CPU, starting from the baseline to Bit sliced macro

 baseline macro 32, metal layers 3, die 550 × 600 μm

add timing

add CTS

add std cells

add logistic prob of wins

Bit sliced macro 28, metal layers 9, die 690 × 750 μm