HW#6 A* Circuit Optimization

 本次作業詳細說明

  課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject HW#6 ［your id, your name]

1. Design a Two-Stage BJT Amplifier according to goals specified using A* (Parameters to optimize RE1, RC1. RE2. RC2) 

A* search for optimization, share  (c_mu=3 pF, c_pi=22 pF)

2. Optimize LM3886 class AB audio amplifier IC using A* (Parameters to optimize: resistors except the load) 

LM3886

A Search Setup*

• State space: 5 components × 5 E12 values each = 3,125 possible states
• g(n): actual steps taken from the start configuration
• h(n): circuit performance cost (the heuristic) — sum of 5 weighted penalties
• f(n) = g + h: A* priority queue ordering

Cost function (5 components, all minimized):

• Gain: quadratic penalty for deviation from 26 dB (20×)
• f_low: penalty if low-frequency cutoff exceeds 10 Hz
• f_high: penalty if high-frequency cutoff falls below 100 kHz
• Bias: penalizes Rb1 ≠ Rb2 (asymmetric thermal tracking)
• Re stability: log-scale penalty away from 0.47 Ω optimum

Weight/ Forms

Are Re1 and Re2 Always Equal?

the architecture inside the LM3886 and TDA7293

optimizer A* (share)

Lessons learned from AI use

Lesson 1

Design a Two-Stage BJT Amplifier (Parameters to optimizeRE1, RC1. RE2. RC2)

Note this is a degenerate model 

A* search for optimization, share 4-parameter (for bypassed model c_mu=3 pF, c_pi=22 pF) note: goal reached is actually current step, not current best

revised to OCT  model  A* search for optimization, share 4-parameter (for bypassed model c_mu=3 pF, c_pi=22 pF)

using 2N2222 parameters (share)

Lesson 2

 Schematic 

Slides

Handouts

Lesson 3

MNA verification 

(a) Degenerative/NonDegenrative ＯＣＴ  Global Exhaustive Search/A*

(b) plus MNA-based Freq sweep

HW#5 LNA Optimization

1, 2 任選一題

本次作業詳細說明

1. Make a GD/(A*)+MNA Optimizer on a Apple C1 LNA Die

Hint: artifact, share

DE+MNA Optimizer on Die artifact

2. To achieve the 15-20 dB gain target and improve the LNA performance to match the schematic specs, use Differential Evolution Optimization to optimize the LNA performance.

Must verify your results to meet spec and parameters have to be realistic.

Hint: (DE+MNA Optimizer on Die artifact) 

demo (transfer function), ngspice, MNA of LNA

 

Want to get these figures, see the Claude share. (Opus 4.6)

HW#4 RF IC Design

建議工具

使用 Claude Sonnet 4.6 推理模式(手動切換，免費用戶額定時間內只能使用三次)

使用 ChatGPT 5 推理模式(自動切換)

使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)

How to publish a Claude artifact

How to share a ChatGPT link

How to share Gemini Link

Content share 作業繳交格式

• share only link, pure text, markdown (md)
• no attachments accepted, no html, screen dump, or png
• non-compliant homework will be rejected and returned to you

課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject HW#4  [your id, your name]

Study Apple C1 Architecture

(a) On Claude, Run NGSpice for the LNA using given parameters. If the results do not match, explain why.

(b) Run an MNA simulation (Modified Nodal Analysis, as used in Cadence Spectre engine). Optimize the IC design to meet specs.

 

Optimized parameters (share)

running ngspice in Claude VM (amazing story)

initial parameters (MNA)

optimized parameters (share)

(c)  Perform DRC (Design Rule Check) for the  3.5 GHz LNA. If it is not entirely design rule compliant, redesign to make the layout more DRC driven.

(DRC, share) (DRC-driven, artifact)

Follow up of HW#3, Placement

PA Placement

original, fixed (hardcoded), SA 1, QP, QP+SA

PA Parameter Optimization

original (analytical), Hessian, MNA (post QP+SA)

PA Lessons, PA Verified by by computing the exact KCL residual at its converged solution, not because of blow up of MNA (share)

PA issues system crash, reality check, UI design

LNA reality check in simulator, prompt for spec compliance

 

LNA v3 (closed-form), V3 pathway to tape-out (advanced, ok omitted)

Overall

1 What is simulated annealing? shown on hyperfunctions comparing to other algorithms

HW#3 IC Design with Advanced AI

建議工具

使用 Claude Sonnet 4.6 推理模式(手動切換，免費用戶額定時間內只能使用三次)

使用 ChatGPT 5 推理模式(自動切換)

使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)

使用 Grok 4 推理模式(自動切換)

---

How to publish a Claude artifact

How to share a ChatGPT link

How to share a Grok link

How to share Gemini Link

Content share 作業繳交格式

• share only link, pure text, markdown (md)
• no attachments accepted, no html, screen dump, or png
• non-compliant homework will be rejected and returned to you

課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject HW#3  [your id, your name]

 1.  Study Apple C1 Architecture

(a) make

LNA schematic (TSMC N7 製程的完整設計流程，包含完整元件表、元件值推導公式、die 面積估算) LNA=Low Noise Amplifier

(b) make

LNA Die

prompts

(c) Build

LNA Optimizer (SMITH Chart, Frequency Response)

Prompts, Cont. Prompts

(d) Build a Simplified (closed-form) LNA optimizer on Die, 3.5 GHz LNA TSMC N7. 

Prompts, Cont. Prompts (same as last)

(e) Build an MNA model (Modified Nodal Analysis, as used in Cadence Spectre engine)  to optimize. Must verify your results to meet spec and parameters have to be realistic.