HW#8 PLL

本次習題基本說明

進階說明

課堂練習 

Deadline: Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#6 [your id, your name]

任選一題

1. (a) Build a 9.0 GHz 65 nm Fractional-N PLL Synthesizer with NM Optimization 

(b)  Cross check your PLL  by MNA

Hint: What is NM method? NM Algo

2.

(a) Build Apple C1 ADPLL — 7.0 GHz (spec) with A* optimization, TSMC N7

Apple C1 ADPLL — 7.0 GHz  

(b) Cross check your Apple C1 ADPLL  by MNA

Common issues in BJT diff pair

BJT diff pair

Routing

(by TA)

1. unfinished routing

2. one stage diff pair 是沒有 miller 電容 cc

miller 電容在 stage 2 

Parameter Optimization

 (by TA)

1. SA 是無效的    

檢查sa 效能 

2. 檢查是否合規 

gain 47.6 db 不夠

PM 0 很危險，不穩定

GBW 太大

設計目標 (3.3V):

Ad ≥ 50 dB  |  CMRR ≥ 80 dB

GBW ≥ 100 MHz  |  PM 55°–75°

Vos ≤ 1 mV  |  Pd ≤ 20 mW

Poly R: 250 Ω/sq (±20%)

MIM C: 1 fF/μm² (±15%)

refer to sample

HW#7 Analog IC Design

課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject HW#6 [your id, your name]

任選1題

1  (a) A BJT Differential Pair IC Die  (share) is incorrectly designed. Fix the die. 

(b) Make a schematic

(c) Do parameter optimization via SA (simulated annealing)

(d) Placement & Routing for the die

For example you may use Quadratic Placement  & ILP+PathFinder+A* Routing

2. Design 2-stage diff pair (share from very simple diff pair)

(a)  Make a schematic,  

(b) Draw a  silicon die, considering Miller Compensation, 

(c) Do P&R (Placement & Routing) for the IC

健康照護科技專題(二) Syllabus 2026 Fall

 (切換完整版課綱)

開場

Unit 1: AI Computer Vision

CNN (Convolutional Neural Networks) Handwashing

YOLO  (You Only Look Once) YOLOv7 list

ViT (Vision Transformers) wafer defects heat map comparison

VLM (Vision Language Models) nutrition analysis

Tesla AI Vision

HW#1 AI in Computer Vision

Unit 2: 盲人環境輔助理解，空間導航

空間資訊與識別輔助 

盲人導航影像辨識 (基礎)

真實世界 3d 模型製作

3d 導航(why 3D)

HW#2 Understanding environments

• 
  

Unit 3: 3d障礙偵測演算法

3d障礙全域分析

障礙偵測(Recast 原理)

Simulating A Navigation Assistant with sonar 

HW#3 Obstacle detection

Unit 4: 避障演算法

Voronoi an introduction, Voronoi for Place Names 

Voronoi 2D navigation (show Voronoi) (Rural Road 2d)

Voronoi-based Safe Routing Planning (Country Alley  2d)

Voronoi waypoints for navigation (share) (Campus Alley 3d) vs. non Voronoi 

3D Voronoi障礙偵測 with A*

A* search for Voronoi Navigation around moving obstacles

Unit 5: 環境安全檢測與評估視覺化 using Claude

Hazard detection (環境危害偵測)

意外事件預測與模擬

Home Hazard chain identification and animation （居家危害鏈偵測與危害視覺化）

Unit 6: 

Unit 7: AI for Game Designing

Games

• 體感洗手練習遊戲
• AI打地鼠遊戲
• 跳舞評分機
• 訊息處理，心智障礙生活輔助 (games for health)

Unit 8 Space-Time Evolution

• Geological evolution of Taiwan

Unit 9 Advanced Prompts

How to scale up: Compound Artifacts

• 如何合成複雜創作 

Unit 10 

AI for Academic Documentation

• AI 論文寫作與研究創新
• AI 論文寫作 (研究、草稿、潤飾、數據分析)
• 選用模型
• 寫作指南
• 練習: Writing academic papers
• 練習: Enhance Writing by AI 1
• 練習: Advanced Writing by AI 2

__________________________________________________________________

規模 9.0 程式設計的地震 

Anthropology

• Human migration

Design

• Floor plan 
• 3D tour

Biology

• Cat coat colors: 貓的花色遺傳模擬
• 生物呼吸中的量子效應互動模擬

6/2 AI for naturalistic modeling

• Fractals

___________________________________________________________

Prompt Engineering Guide

Japan in Geological evolution

Document Editing Prompt

Prompts for scientific accuracy

• Simulating lasers
• Semiconductor visualization (Blue LED)

• Scientific animation

  Financial Analysis in AI

HW#6 A* Circuit Optimization

 本次作業詳細說明

  課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject HW#6 ［your id, your name]

任選一題

1. Design a Two-Stage BJT Amplifier according to goals specified using A* (Parameters to optimize RE1, RC1. RE2. RC2) 

A* search for optimization, share  (c_mu=3 pF, c_pi=22 pF)

2. Optimize LM3886 class AB audio amplifier IC using A* (Parameters to optimize: resistors except the load) 

LM3886

A Search Setup*

• State space: 5 components × 5 E12 values each = 3,125 possible states
• g(n): actual steps taken from the start configuration
• h(n): circuit performance cost (the heuristic) — sum of 5 weighted penalties
• f(n) = g + h: A* priority queue ordering

Cost function (5 components, all minimized):

• Gain: quadratic penalty for deviation from 26 dB (20×)
• f_low: penalty if low-frequency cutoff exceeds 10 Hz
• f_high: penalty if high-frequency cutoff falls below 100 kHz
• Bias: penalizes Rb1 ≠ Rb2 (asymmetric thermal tracking)
• Re stability: log-scale penalty away from 0.47 Ω optimum

Weight/ Forms

Are Re1 and Re2 Always Equal?

the architecture inside the LM3886 and TDA7293

optimizer A* (share)

Lessons learned from AI use

Lesson 1

Design a Two-Stage BJT Amplifier (Parameters to optimizeRE1, RC1. RE2. RC2)

Note this is a degenerate model 

A* search for optimization, share 4-parameter (for bypassed model c_mu=3 pF, c_pi=22 pF) note: goal reached is actually current step, not current best

revised to OCT  model  A* search for optimization, share 4-parameter (for bypassed model c_mu=3 pF, c_pi=22 pF)

using 2N2222 parameters (share)

Lesson 2

 Schematic 

Slides

Handouts

Lesson 3

MNA verification 

(a) Degenerative/NonDegenrative ＯＣＴ  Global Exhaustive Search/A*

(b) plus MNA-based Freq sweep

HW#5 LNA Optimization

1, 2 任選一題

本次作業詳細說明

1. Make a GD/(A*)+MNA Optimizer on a Apple C1 LNA Die

Hint: share

2. To achieve the 15-20 dB gain target and improve the LNA performance to match the schematic specs, use Differential Evolution Optimization to optimize the LNA performance.

Must verify your results to meet spec and parameters have to be realistic.

DE+MNA Optimizer on Die