HW#14 Robot and BLV Navigation

成績分布草案(EX#14尚未統計)

課堂練習 

Deadline:  Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#14 [your id, your name]

 3 選一

1. 參考Voronoi navigation app，製作以下場景的導航

task 1: make an entrance/exit. make the auto-navigation route deliberately exit through this gate (e.g., a waypoint placed just outside on the brick path) and go to central woods as destination.

task 2: set FPV (first-person view) and maintain horizontal view angle

task 3: show Voronoi Waypoints for navigation

提示：給還不熟悉Claude 的同學，如何套用既有導航系統到這個溜冰場情境(如照片)，已經會套用artifact 同學可以跳過

如何套用 https://claude.ai/share/8ac9c5a7-4944-41e7-a1af-027635b14dac

2. Implement Voronoi-based navigation for robots or BLV users

Non-Voronoi Navigation

3. Benchmark the two static vs. dynamic Voronoi-based navigation. 30 seeds.

Voronoi start-up A* + Repelling

dynamic voronoi

Follow up HW#13

 Problem 1

以下是比較不同演算法得出的繞線以及比較不同繞線的電路效能

Trace Routing Errors and Repairs router optimization （original by Ms. Wu）

A* vs Dijkstra side-by-side comparison originally by Ms. Kuo

Problem 2

suggestions

- Add a short note on how CL1 and CL2 set the load capacitance the crystal sees: CL = (CL1*CL2)/(CL1+CL2) + Cstray. With 22 pF caps this lands near the common 12 to 18 pF crystal spec once stray is included, and stating it explicitly ties your part choices to the datasheet.

pierceCalc

Consider analysis of heatmap

trace, 3d, heat map＊ heat map by me, trace route and 3D by Mr. Su

HW#13 Circuit Optimization on PCB

課堂練習 

Deadline:  Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#13 [your id, your name]

1. Optimize trace routing for the Differential Pair Circuit on PCB 

trace routing, share (artifact, more accurate schematic)

Steps

Starting from the imperfect design, complete the trace routing. Do trace routing ( 參考 share, share 2, share 3)

我是希望你們可以自行變換

無論是優化，更換演算法，UI 都可以，總之不是複製

2. 設計Crystal 石英振盪電路的PCB

 (slides) schematic

除了ＰＣＢ視覺化，我是希望可以做一下 sensitivity analysis 或是 heat map

(3, 4 任選一題來做)

3. 使用鑽孔路徑演算法進行以下PCB 鑽孔(演算法 提供參考)

PCB 1

4. 

PCB 2

甚麼是 TSP?

Traveling Salesman Problem 簡稱TSP

 (一個推銷員要拜訪所有客戶城市，每個城市只能拜訪一次，最後要回到出發城市，請為他/她計算最短的拜訪路徑)

TSP在工業界有重要應用，包括物流（UPS/Amazon配送路線優化）、製造業（電路板鑽孔、機器人組裝路徑）、電信（網路路由、線路安裝）和能源（電網維護、管線檢查）。凡是需要造訪多個地點同時最小化成本、時間或距離的場合都適用。現代變體能處理容量限制、時間窗口等實際約束。企業使用OR-Tools、Gurobi等專業軟體解決這些問題，透過優化倉儲揀貨、切割模式、3D列印路徑和車隊管理等作業，往往能節省數百萬成本。

(樸素) Visualize TSP (Traveling Salesman Problem) by A* search 使其可以改變網路節點個數

(美學) 視覺化 A* for Traveling Salesman Problem 使其可以改變網路節點個數

Search for a Class-F RF PA. (Follow up HW#12)

 我用 Claude cowork 找了滿足條件的 Class-F

artifact

fitness function disfavors class-F (HD3 floor constraint wants it be class-AB), relaxed during search

class-F note: the two solutions are within the same basin

s11, s22 repair, dashboard

IEEE AI Policy

 

IEEE 作者通訊摘要

AI 使用規範（重點）

作者責任： 文章中所有內容（含 AI 生成部分）的正確性與抄襲檢查，由作者負完全責任。

該做的事：

• 揭露所有 AI 使用情況，於 Acknowledgements 區段註明工具名稱與使用方式
• AI 工具可列入參考文獻，但前提是作者已獨立驗證內容正確性
• AI 生成的模擬/仿真資料須清楚標示

不該做的事：

• ❌ 不可將 AI 系統列為作者
• ❌ 不可將 AI 工具作為引用來源（除非已獨立驗證）

例外： 若僅以 AI 改善語言（grammar/editing）且不改變語意或新增智識內容，可不揭露。

小提醒： 用 AI 編修文字時，不要把參考文獻區段一起丟進去，以免被竄改。詳見 IEEE PSPB Operations Manual 第 8.2.1.B10 節（p.107）。

Doherty RF PA design

  Doherty paper, level of physics

artifact

HW#12 PnR for Apple C1 PLL and RISC Core CPU

本次習題基本說明 PLL

進階說明 PLL

講義

on Apple C1 PLL

on Modern Placement Algorithms

課堂練習 

Deadline: Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#12 [your id, your name]

任選一題

 1. Use this physics model to identify a high efficiency Class F RF amplifier. ASAP7 Class-F (auto-load)

dual attractors

basin transitions

Amplifier class (harmonics in PA design)

2.（a)Build a model of Apple C1 ADPLL — 7.0 GHz (spec) with A* and NM Version, NM cross checked by MNA,  

(b) Enhance the Apple C1 PLL model with DTC by building an Optimizer with MNA-powered trajectory. share, DTC-Solver

You may refer to schematic, architecture and timing, DTC-TDC Timing (share)

Apple C1 ADPLL — 7.0 GHz  (C1 is N4P)

Head-to-head

3. Write an algorithm for Macro Routing for a RISC core CPU, starting from the baseline to Bit sliced macro

 baseline macro 32, metal layers 3, die 550 × 600 μm

add timing

add CTS

add std cells

add logistic prob of wins

Bit sliced macro 28, metal layers 9, die 690 × 750 μm

Two-stage Class-AB RF PA driver: parameter optimization GaN

 GaN, "Calibrated for 0.25 µm GaN-on-SiC RF process (Wolfspeed G2 / WIN NP25 class)" for base station

artifact (topology change, single device)

LNA Chip Physics Model, PnR

 

LNA Physics Model

artifact

LNA PnR

artifact

artifact

HW#11 RF IC Placement & Routing

  Benchmark  Two-stage Cascode Class-AB RF power amplifier targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Experiment with 30 seeds

Measure success, congestion, wirelength, overlap pairs (before/after)

Placement style 1

Placement artifact style 2

benchmark

 

Benchmark the P&R for OP 741.

Experiment with 3 seeds

Measure success, congestion, wirelength, overlap pairs (before/after), Vin length match

Placer & Router for OP 741

benchmark

HW#10 RF PA Driver Design (physics vs. closed-form)

 1. Benchmark the three designs of RF PA Drivers

2-stage RF PA driver 

Closed-form Optimizer with Load-Pull Contours 

Performance-first Thermal build  ∠Γ_3f₀ phase (deg) · open=0, -170 deg

Margin-first Thermal build ∠Γ_3f₀ phase (deg) · open=0, -170 deg

Using Cowork or Claude.ai, benchmark the three models. Experiment with 5 seeds. For each seed, optimize the circuit design using built-in A* and then NM. 

For each seed, record metrics from the cascaded optimizers: 

Compare Closed-Form vs. margin-first build vs. comprehensive model. 

-Tabulate Gain, Pout, PAE, OP1dB, S₁₁ (5 metrics × 10 seeds = 40 cells).

-Identify which metric the closed-form most over- or under-estimates.

Cross-check both thermal designs: compute junction temperature rise ΔT_j at peak Pout. Which design runs cooler? By how many °C?

-Build a 2×2 comparison table: rows = {Performance-first, Margin-first}, columns = {Fitness, min-spec-margin (dB), ΔT_j (°C), PAE @ 6dB back-off}.

Visualize all of your data

Supplemental

Margin vs. Performance builds

design choices 

Training Pipeline in Claude Cowork- OPC lithography hotspot detection code

wrap in slides

 

HW#9 RF PA Driver Design (Comparing optimization algorithms and pipelines)

 課堂練習 

Deadline: This Saturday at 23:59

Send all the share links to  me chang212@gmail.com by email with subject HW#9 [your id, your name]

只要做第一題

1. Benchmark the three algorithms (GD, NM, A*) and their cascades (one designed by you and the other design by AI )

• For the five methods, each runs with 10 seeds
• Tabulate Gain, Pout, PAE, OP1dB, S₁₁ (5 methods = 5 tables, each table with 5 metrics × 10 seeds = 40 cells).
• Visualize all of your data

Two-stage Cascode Class-AB RF PA Driver targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Build Sub 6 GHz Power Amplifier Optimizer with Die Synced

share, artifact (Closed-Form)

Benchmark using Claude, Benchmark results