In February 2025 Apple shipped its first in-house cellular modem, the C1, in the iPhone 16e. Apple described its baseband as a 4 nm chip and its transceiver as a 7 nm chip [1]. This page follows one block of such a transceiver, the low-noise amplifier (LNA), the first amplifier after the antenna, here for 5G NR band n78 (3.3–3.8 GHz) [6]. The interactive pages linked below were made with Claude in February and March 2026. They run from architecture diagrams to a schematic, a 3D die view and several circuit optimizers, with teaching pages on the Smith chart and S-parameters. Apple has not published its LNA, so the circuit is a teaching design in a 7 nm FinFET process, not Apple's.
In November 2026 every page was checked and an enhanced copy made. The copies are collected on one page, 3.5 GHz Cascode LNA Pages, which shows each copy next to a list of what changed and a link to the original. Below, each page is linked as it was, followed by its copy.
- One model for every page. The original optimizers each had their own constants, and several of their numbers did not follow from their inputs. The copies share one device and circuit model (Table 2), and its JavaScript code agrees with a separate Python implementation to machine precision.
- The input match was the main error. The optimizers added the 200 fF of pad and ESD capacitance to the transistor's gate capacitance and then took the input resistance as gmLs/C. Only the current through the gate capacitance is amplified, so that resistance is several times too high. The design that the v2.2 optimizer shows with S11 = −21.5 dB has S11 = −5.8 dB in the shared model, and a noise figure of 0.97 dB instead of 0.35 dB (Table 3).
- What the original slider ranges allow. Searched over the same five sliders, the best design reaches 20.6 dB gain, 0.75 dB noise figure and S11 of −18.1 dB at 3.5 GHz (−11.0 dB at worst in the band), with IIP3 −5.3 dBm at 5.0 mW. Three of the five parameters end at the top of their range, and the optimizers on the pages stop at local optima well below it.
- A design outside the sliders matches the whole band. The corrected design guide adds 150 fF between gate and source, uses an Ls of 826 pH (the sliders stop at 500 pH) and matches the output with two capacitors. It holds S11 below −15 dB across n78, with 19.0 dB gain and a 0.93 dB noise figure at 3.0 mW.
- The EX#8 design is the reference. A later n77 design (3.3–4.2 GHz), with its own circuit simulators and a layout, reaches a post-layout noise figure of 1.18 dB and S11 ≤ −10.8 dB across the band at 7.79 mW. Section 6 compares it with the pages here.
Apple's chips · The LNA · One model · Closed-form optimizers · Circuit-solver optimizers · EX#8 · Teaching pages · How it was built · Limits · All pages
Updated 4 November 2026. The original post of 6 February 2026 is kept at its own address with all its links.
1. Apple's wireless chips
Apple is replacing the wireless chips it buys with its own (Table 1).
| Chip | Announced | What it is | First devices |
|---|---|---|---|
| C1 | 19 Feb 2025 | 5G modem: 4 nm baseband, 7 nm transceiver; sub-6 GHz only, no mmWave [1, 2] | iPhone 16e |
| C1X | 9 Sep 2025 | Second modem. Apple: up to twice as fast as C1, and 30% less energy than the modem of the iPhone 16 Pro; no mmWave [3] | iPhone Air; cellular M5 iPad Pro (15 Oct 2025) [4] |
| N1 | 9 Sep 2025 | Wi-Fi 7, Bluetooth 6 and Thread chip, replacing Broadcom parts [5] | iPhone 17 line, iPhone Air, M5 iPad Pro |
| C2 | 9 Sep 2026 | Next-generation modem. Apple: faster uploads than C1X at 15% less energy, and mmWave (n258, n260, n261) in the US; process not disclosed [7] | iPhone 18 Pro, iPhone Duo; the US iPhone 18 Pro Max lists no Apple modem [7] |
TechInsights identified the C1 baseband die as APL1114 and published a floorplan [2]. The transceiver's circuits, its LNAs among them, are not public.
Five pages set the scene. The chip replacement roadmap (copy) lays out the plan to replace Qualcomm's modem, Broadcom's Wi-Fi and Bluetooth chip and the Skyworks and Qorvo front-end parts. The C1 transceiver architecture (copy) and the C1 architecture (copy) pages draw the modem from baseband to antenna. Baseband and transceiver (copy) asks why the baseband moves to 3 nm and below while the transceiver stays at 6 to 7 nm, and RF CMOS and 65 nm LP (copy) is a set of slides on RF CMOS processes and a 9 GHz PLL.
The copies date each chip to Apple's announcements, mark reports as reports and give a source for each figure. The roadmap said that 65 nm LP chips power iPhone radios. That held only for the Wi-Fi chips of 2009 to 2011, so a panel now gives each part's process: 4 nm for the C1 baseband, 7 nm for its transceiver, GaAs HBT for the power amplifiers and RF-SOI for the switches. Fees and spending figures with no source are gone. The architecture page drops specs that no source supports, such as a PCIe 3.0 link to the SoC and dual-frequency GPS, and adds C1X, N1 and C2. The transceiver page is labelled a generic teaching model, and its LNA card, whose 0.7 nH and 35 pH resonated at 29 GHz, now carries the design of Section 4. The baseband page notes that SRAM, which it said shrinks with each node, has nearly stopped: the N3E bitcell is the N5 one, 0.021 µm². The slides correct the history of iPhone radio processes and compute their PLL loop filter, whose original 335 nF capacitor would have needed 168 mm² of chip.
2. The LNA
The LNA is a cascode with inductive source degeneration. Transistor M1 amplifies, with inductor Ls from its source to ground. M2, stacked on top, isolates the output from the input. Lg brings the signal from the pad to the gate of M1, and Ld at the drain tunes the output. Without pad and ESD capacitance, the input impedance is
so the input resonates where ω0²(Lg + Ls)Cgs = 1, and there it looks like a resistor of ωTLs, which Ls sets to 50 Ω [8]. The LNA schematic (copy) draws the circuit with these equations, the design flow (copy) derives every component value and estimates the die area, the spec sheet (copy) lists the targets, and the die view (copy) builds the circuit in 3D (Fig. 1).
The design flow's own numbers do not resonate. For its transistor, 40 µm wide with Cgs = 28 fF, Lg + Ls must be 1/(ω0²Cgs) = 73.9 nH at 3.5 GHz, where the flow gives 740 pH, the value for 35 GHz. Its Ld of 2.6 nH needs 0.80 pF at the drain. In the shared model the flow's values give S11 of −0.1 dB, 11.4 dB gain and a 1.74 dB noise figure, and the circuit is only conditionally stable (K falls to 0.43). A real design adds capacitance between gate and source, as EX#8 does with 205 fF, or uses a much wider transistor.
The copy of the flow redoes the design in three steps: the textbook formula, then the ESD capacitance, then the circuit solve. It keeps W = 40 µm and 4 mA, adds Cex = 150 fF from gate to source and moves Lg (6.12 nH) off the chip, with Ls = 826 pH. Ld = 2.6 nH is tuned by 512 fF, and a 282 fF series capacitor matches the output to 50 Ω. The design gives 19.0 dB gain, a 0.93 dB noise figure, S11 below −15 dB across n78, IIP3 −2.5 dBm and 3.0 mW, and it is stable (K ≥ 1.75). The bias resistor goes from 8 kΩ, which added 0.20 dB of noise, to 50 kΩ, and the die area is 0.113 mm² with Lg off the chip.
The schematic copy draws this design with every part, the pad and ESD capacitances included, and explains each part on a click. Its gain formula now gives S21 into 50 Ω, 19.5 dB against the circuit solve's 19.0 dB; the 30.8 dB that the original called gain is the drain's unloaded voltage gain. In its noise budget the loss of Lg is 45% of the excess noise and the channel noise of M1 42%. The spec sheet now uses the spec that all copies share and scores real designs instead of showing typed-in scores: 96.5% for the corrected guide, 92.8% for the best design of Section 4, 69.0% for the v2.2 design and 30.5% for the guide's original values. The die view draws whichever design is picked, with spirals sized from their inductance and transistor fingers from the fin count.
3. One model for every page
The optimizers in the next two sections solve the same circuit, but each original had its own constants and formulas. The copies share the model in Table 2. Where a page has to differ, as the N16 variant does, it says so.
| Quantity | Original optimizers | Shared model |
|---|---|---|
| Fins | W / 7 nm: 4286 fins for 30 µm | 0.110 µm of effective width per fin: 273 fins |
| Gate resistance Rg | about 0 Ω | 270 Ω / fins, 1 Ω at 30 µm |
| gm/Id | constant 12.5 S/A | 12.5 S/A at 100 µA/µm, higher at lower current density, lower at higher (velocity saturation) |
| fT | gm / 2π(Cgs + 200 fF of pad) | gm / 2π(Cgs + Cgd) |
| Pad and ESD | 200 fF added to Cgs | 30 fF at the pad, 170 fF from gate to ground |
| Input resistance | gmLs / (Cgs + 200 fF) | from the circuit solve |
| Inductor loss | Ld only (Q 12) | Q 25 for Lg, 15 for Ls, 12 for Ld |
| Noise figure | channel noise plus fixed terms (0.2 f/fT, 0.1 |W − 40 µm|/40 µm); no inductor loss | every source: resistors and inductor losses, channel and induced gate noise of both transistors with their correlation (γ 1.2, δ 3.5, |c| 0.395) |
| Gain | gm · min(QωLd, 500 Ω), labelled S21 | S21 into 50 Ω, no output match |
| IIP3 | (4/3)Vov²/Rs plus a 4 dB cascode bonus and a degeneration bonus | two-tone, from the transistor's second- and third-order terms [9] |
| Power | 2 · VDD · Id | VDD · Id, VDD = 0.75 V |
4. Closed-form optimizers
The first optimizers score a design from hand equations. LNA Optimizer (copy) (v2.2) tunes the five sliders of Fig. 2 by gradient descent or A* search [10], with a Smith chart, a radar chart and a frequency response. The synced versions add the die of Fig. 1, which morphs as the sliders move: die and sliders synced (copy), with Nelder–Mead added (copy) [11], N16 (copy) for TSMC 16 nm and UI with synced sliders (copy).
| v2.2, page | shared model | synced, page | shared model | |
|---|---|---|---|---|
| Design: W, µm | 30 | 50 | ||
| Id, mA | 2.5 | 3.5 | ||
| Lg, nH | 9 | 8 | ||
| Ls, pH | 350 | 250 | ||
| Ld, nH | 2.5 | 2.5 | ||
| Gain (S21), dB | 23.88 | 17.1 | 26.8 | 19.4 |
| Noise figure, dB | 0.35 | 0.97 | 0.31 | 0.84 |
| S11 at 3.5 GHz, dB | −21.46 | −5.8 | −23.5 | −6.8 |
| S11, worst in 3.3–3.8 GHz, dB | – | −3.8 | – | −4.8 |
| IIP3, dBm | 4.63 | −13.1 | 3.9 | −11.5 |
| Power, mW | 3.8 | 1.9 | 5.3 | 2.6 |
| gm, mS | 31.25 | 34.3 | 43.8 | 52.2 |
| fT, GHz | 21.62 | 140 | 27.9 | 128 |
| Input resonance, GHz | 3.43 | 3.63 | – | 3.61 |
The largest gap is the input match. The pages add the 200 fF of pad and ESD capacitance to Cgs and keep the input resistance gmLs/Cin: about 47 Ω for the v2.2 design. But the ESD capacitance shunts the gate to ground, and only the current through Cgs is amplified. The resistance becomes roughly gmLsCgs/(Cgs + Cesd)², about 9 Ω here, plus 7.9 Ω of series loss in Lg. The circuit solve gives 17 Ω, and S11 is −5.8 dB. The other rows move for three reasons. Gain is S21 into a 50 Ω load, where the page multiplied gm by a tank resistance of up to 500 Ω. IIP3 comes from the transistor's nonlinearity, referred to the source through the input network, instead of a formula with fixed bonus terms. And the noise figure now counts the loss of Lg, which is 63% of the excess noise of the v2.2 design.
With the shared model, the best design within the original slider ranges, found by differential evolution [12] and scored with the spec of the later pages, is W = 80 µm, Id = 6.67 mA, Lg = 7.72 nH, Ls = 500 pH and Ld = 5 nH, at a score of 92.8%. It gives 20.6 dB gain, 0.75 dB noise figure, S11 of −18.1 dB at 3.5 GHz and −11.0 dB at worst in the band, IIP3 −5.3 dBm and 5.0 mW. The optimum is flat: the closed form puts it at 6.5 mA and 8 nH, which the circuit solve scores 92.7%, with S11 of −20.4 dB at 3.5 GHz and −10.6 dB at worst in the band. W, Ls and Ld sit at the top of their ranges. The wider transistor raises Cgs against the fixed ESD capacitance, and the larger Ls raises the input resistance. Ld cannot tune the output at all: with the drain capacitance, 1 to 5 nH resonates between 6 and 16 GHz, and 3.5 GHz would need 15 to 18 nH.
The copies keep each page's optimizers, sliders and layout, and compute every number from a closed form of the shared model. A check against the circuit solver stays on screen: over 450 test designs the two differ by at most 0.13 dB, and a toggle runs the optimizers on either one. The original optimizers stopped after their first step, because the start designs already scored above their 97% stop. Now they run, and reach 70 to 80%; the Best (DE) button shows the 92.7% design. The die of the synced pages follows the values, with spirals sized from their inductance by the modified Wheeler formula [14] and transistor fingers from the fin count. The N16 page says it is a teaching variant with assumed constants (VDD 0.8 V, 0.080 µm per fin); the designs it scored 98% score about 65% once its model is corrected.
5. Circuit-solver optimizers
The later pages solve the whole circuit by modified nodal analysis (MNA) [13] at each frequency, with noise from every source. MNA Optimizer on Die (copy) tunes all parameters by gradient descent or A*, and DE + MNA Optimizer (copy) by differential evolution. Super (copy) combines the features of the others, and the comparisons ask what differs between the three implementations (what difference (copy)) and which teaches better (educational values (copy)). Merit of Figure (copy) optimizes a noise-cancelling LNA across several bands [16].
The circuit solve gets the input match right, but the MNA pages kept other shortcuts of the closed-form pages. v3.2 still divided gm by Cgs + Cesd for fT (31.6 GHz; 128 GHz in the copy), counted power as 2 · VDD · Id and fins as W/7 nm, which left 0.002 Ω of gate resistance, and added fixed bonuses in dB to IIP3. It also counted noise twice, adding thermal noise of the output resistance, which the channel noise already covers, and a substrate term that was not in the circuit. In the copy its IIP3 goes from +4.0 to −11.5 dBm, which two-tone harmonic balance confirms (−11.46 dBm). The MNA + DE page estimated S22 with a closed form (−20.0 dB). Solved in the circuit, its default design has S22 of −0.75 dB and S11 of −5.1 dB; its Lg slider of 1 to 3 nH could not resonate the gate, and its title said 5 GHz. In Super (v4.3) the hand-analysis noise chain now tracks the circuit solve, 0.835 dB against 0.826 dB where it was 0.678 dB against 0.759 dB, and the thermal map, which stopped after 100 sweeps before it converged, matches a direct solve: its peak is 6.4 K, not 4.6 K.
Merit of Figure computed each output from its own formula, and two of them, S22 (−11.7 dB) and the minimum noise figure (0.18 dB), came out the same for every design. The copy solves the whole noise-cancelling circuit as one 8-node MNA. Its default n77 design then has a 2.38 dB noise figure instead of 1.09 dB and 15.1 dB gain instead of 19.7 dB, and its 1.5 dB noise spec cannot be met: the best design found has 1.64 dB. The two comparisons are corrected where the code disagrees with them. Using the long-channel γ = 2/3 without induced gate noise lowers the noise figure by 0.09 to 0.26 dB, not 1 to 1.5 dB, because the loss of Lg dominates; the correlation term moves it by about 0.02 dB either way; and the channel noise of M1 leads the noise budget in only 11 of 1,707 matched designs on a grid of 39,200.
6. The EX#8 design
EX#8 (copy), linked as the original post's update, designs an LNA for the wider band n77 (3.3–4.2 GHz) at 0.8 V with its own MNA and harmonic-balance simulators, a predictive FinFET model and a layout of 0.445 mm². Table 4 sets it beside the best design of Section 4 and the corrected design guide of Section 2. Like the guide, it adds capacitance between gate and source, and it has the output match that the optimizer pages leave out, which is why their S22 stays near −1 dB.
| Best five-slider design | Corrected design guide | EX#8, after layout | |
|---|---|---|---|
| Band | n78, 3.3–3.8 GHz | n78 | n77, 3.3–4.2 GHz |
| M1 | 80 µm, 6.67 mA | 40 µm, 4 mA | 1008 fins, 9.4 mA |
| Cex | – | 150 fF | 205 fF |
| Lg, Ls, Ld | 7.72 nH, 500 pH, 5 nH | 6.12 nH, 826 pH, 2.6 nH | 5.13 nH, 180 pH, 2.62 nH |
| Output match | none | 512 fF tank, 282 fF series | yes |
| Gain, dB | 20.6 (19.9 in band) | 19.0 (16.4 in band) | 18.4–20.2 |
| NF, dB | 0.75 | 0.93 | 1.18 |
| Worst S11, dB | −11.0 | −15.1 | −10.8 |
| Worst S22, dB | −1.05 | −3.9 | −10.5 |
| IIP3, dBm | −5.3 | −2.5 | ≥ −6.9 |
| Power, mW | 5.0 | 3.0 | 7.79 |
| Score | 92.8% | 96.5% | – |
The shared model is optimistic about Lg. It gives the gate inductor a Q of 25, as a package or off-chip inductor would have. An on-chip spiral has a Q of 10 to 15, and with it the best five-slider design has a noise figure of 1.1 to 1.5 dB; in EX#8 the loss of Lg is 61% of the excess noise.
7. Teaching pages
Matching is easiest to see on the Smith chart: Smith chart explained (copy), an interactive Smith chart (copy) and an automatic L-network matcher (copy). S-parameters on one slide (copy) explains S11, S21, S12 and S22 with an amplifier, and the LNA slides (copy) (in Chinese, for senior high school) go from the MOSFET to the cascode, the N7 process and impedance matching.
Two errors recur in the Smith chart pages. They showed the reflected power as |Γ| instead of |Γ|², 48% instead of 23.4% for a load of 25 + j30 Ω, and their short and open presets were 1 Ω and 500 Ω. The guide's rule that a coil turns the point clockwise holds only for series parts: shunt parts turn the other way, along circles of constant conductance. The matcher's buttons had fixed labels that misnamed its networks (85 wrong labels over 93 test loads), and it gave the wrong condition for shunt-first networks. Its note on the LNA described the gate as inductive and matched by a series Lg and a shunt Ls; the gate is capacitive, and the copy shows it matched by the ESD capacitance and Lg.
The S-parameter slide now states the conditions behind each definition, adds a stability section [15] and shows the S-parameters of the Section 4 design from 1 to 8 GHz. The Chinese slides correct several numbers (a phone's usual maximum transmit power is 0.2 W, or 23 dBm, not 1 W; a signal 10 m away is about −40 dBm, not −30 dBm) and work the Friis formula through with a slider. They replace four charts that were not data, among them a noise-figure curve with an unsourced optimum, with charts computed from the model, and they say plainly that Apple's LNA is not public.
8. How the pages were built
The prompts of the three chats are kept as they were: prompts for the architecture and die pages, prompts and continued prompts for the optimizers. Two chats are shared: the v2.2 optimizer and the synced pages; the third share, of the Merit of Figure chat, no longer opens (checked 3 November 2026). The dev log (copy) records how the model was corrected from version to version. Its copy rebuilds the timeline from the chats' timestamps and recomputes each version's numbers with that version's own code. The circuit solver arrived in v3.0 on 17 March and the split of pad and ESD capacitance in v3.1, not in v2.2.1, which synced the die and sliders and still used the closed form. The low fT of the early pages came from the 200 fF of pad capacitance in its denominator, not from missing velocity saturation. v3.2's noise figure at its default design is 0.84 dB; the 1.2 to 1.6 dB in the log was a forecast in the chat. Figures that no code or chat supports, such as an fT of 319.73 GHz, are marked, and every quotation was checked word for word against its source.
9. What was checked, and the limits
- How the copies were checked. Each copy was opened in a headless browser at desktop and phone widths, with no script errors and nothing wider than the screen, and its numbers were recomputed by script. The shared engine agrees with a separate Python implementation to machine precision, and its IIP3 agrees with two-tone harmonic balance within 0.04 dB on the cascode pages and 0.14 dB on the noise-cancelling page. Facts on the context pages are dated to Apple's announcements, teardowns or named reports, and DOIs were checked against Crossref. Each copy lists its own checks and limits next to its changes.
- Not Apple's design. Apple has not published the C1 transceiver's circuits. Every LNA here is a teaching design in the style of a 7 nm sub-6 GHz receiver.
- A model, not silicon. The shared model is a compact model with textbook noise and nonlinearity terms. Nothing was measured, and only EX#8 has a layout and post-layout numbers.
- What Apple has not said. Apple has not given the process of the C2 or the N1, or the modem of the US iPhone 18 Pro Max, whose spec page lists none; reports say it is Qualcomm's.
10. All pages
[1] eeNews Europe, “Apple moves to its own modem silicon with the C1,” Feb. 2025. link
[2] TechInsights, “Apple custom C1 5G modem floorplan analysis,” 2025. link
[3] TechInsights, “iPhone Air: redefining Apple's wireless strategy,” 2025. link
[4] MacRumors, “Apple debuts new iPad Pro with M5,” 15 Oct. 2025. link
[5] Engadget, “Apple's new wireless chips give it even more control of the iPhone,” Sep. 2025. link
[6] 3GPP TS 38.101-1, NR user equipment radio transmission and reception, Part 1: Range 1 standalone. n77 is 3300–4200 MHz and n78 3300–3800 MHz. link
[7] Apple Newsroom, “Apple debuts iPhone 18 Pro and iPhone 18 Pro Max” and “Apple unveils iPhone Duo,” 9 Sep. 2026; MacRumors, “iPhone 18 Pro and iPhone 18 Pro Max have different modems,” 9 Sep. 2026. link
[8] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, 1997. doi:10.1109/4.568846
[9] B. Razavi, RF Microelectronics, 2nd ed., Prentice Hall, 2011, chapters on nonlinearity and LNAs.
[10] P. E. Hart, N. J. Nilsson and B. Raphael, “A formal basis for the heuristic determination of minimum cost paths,” IEEE Trans. Systems Science and Cybernetics, vol. 4, no. 2, pp. 100–107, 1968. doi:10.1109/TSSC.1968.300136
[11] J. A. Nelder and R. Mead, “A simplex method for function minimization,” The Computer Journal, vol. 7, no. 4, pp. 308–313, 1965. doi:10.1093/comjnl/7.4.308
[12] R. Storn and K. Price, “Differential evolution: a simple and efficient heuristic for global optimization over continuous spaces,” J. Global Optimization, vol. 11, pp. 341–359, 1997. doi:10.1023/A:1008202821328
[13] C.-W. Ho, A. E. Ruehli and P. A. Brennan, “The modified nodal approach to network analysis,” IEEE Trans. Circuits and Systems, vol. 22, no. 6, pp. 504–509, 1975. doi:10.1109/TCS.1975.1084079
[14] S. S. Mohan, M. del Mar Hershenson, S. P. Boyd and T. H. Lee, “Simple accurate expressions for planar spiral inductances,” IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1419–1424, 1999. doi:10.1109/4.792620
[15] J. M. Rollett, “Stability and power-gain invariants of linear twoports,” IRE Trans. Circuit Theory, vol. 9, no. 1, pp. 29–32, 1962. doi:10.1109/TCT.1962.1086854
[16] F. Bruccoleri, E. A. M. Klumperink and B. Nauta, “Wide-band CMOS low-noise amplifier exploiting thermal noise canceling,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 275–282, 2004. doi:10.1109/JSSC.2003.821786
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