HW#12 PnR for Apple C1 PLL and RISC Core CPU

本次習題基本說明 PLL

進階說明 PLL

講義

on Apple C1 PLL

on Modern Placement Algorithms

課堂練習 

Deadline: Saturday at 23:59 (one more week)

Send all the share links to  me chang212@gmail.com by email with subject HW#12 [your id, your name]

任選一題

 1. Use this physics model to identify a high efficiency Class F RF amplifier. ASAP7 Class-F (auto-load)

dual attractors

basin transitions

Amplifier class (harmonics in PA design)

2.（a)Build a model of Apple C1 ADPLL — 7.0 GHz (spec) with A* and NM Version, NM cross checked by MNA,  

(b) Enhance the Apple C1 PLL model with DTC by building an Optimizer with MNA-powered trajectory. share, DTC-Solver

You may refer to schematic, architecture and timing, DTC-TDC Timing (share)

Apple C1 ADPLL — 7.0 GHz  (C1 is N4P)

Head-to-head

3. Write an algorithm for Macro Routing for a RISC core CPU, starting from the baseline to Bit sliced macro

 baseline macro 32, metal layers 3, die 550 × 600 μm

add timing

add CTS

add std cells

add logistic prob of wins

Bit sliced macro 28, metal layers 9, die 690 × 750 μm