This is the original version of this post, first published on 19 April 2026 and kept unchanged below. The current version is SweRV RISC IC Design: Macro Routing from Baseline to Bit-Sliced Buses. The interactive pages linked below are no longer online. Rebuilt copies of every stage, with English labels, are collected at SweRV routing demos.
baseline macro 32, metal layers 3, die 550 × 600 μm
Bit sliced macro 28, metal layers 9, die 690 × 750 μm
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