健康照護科技專題 : 2026

2026年5月20日星期三

Two-stage Class-AB RF PA driver: parameter optimization GaN

GaN, "Calibrated for 0.25 µm GaN-on-SiC RF process (Wolfspeed G2 / WIN NP25 class)" for base station

artifact (topology change, single device)

2026年5月19日星期二

LNA Chip Physics Model, PnR

LNA Physics Model

artifact

LNA PnR

artifact

2026年5月18日星期一

HW#11 RF IC Placement & Routing

Benchmark Two-stage Cascode Class-AB RF power amplifier targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Experiment with 30 seeds

Measure success, congestion, wirelength, overlap pairs (before/after)

Placement style 1

Placement artifact style 2

benchmark

Benchmark the P&R for OP 741.

Experiment with 3 seeds

Measure success, congestion, wirelength, overlap pairs (before/after), Vin length match

Placer & Router for OP 741

benchmark

2026年5月12日星期二

HW#10 RF PA Driver Design (physics vs. closed-form)

1. Benchmark the three designs of RF PA Drivers

2-stage RF PA driver

Closed-form Optimizer with Load-Pull Contours

Performance-first Thermal build ∠Γ_3f₀ phase (deg) · open=0, -170 deg

Margin-first Thermal build ∠Γ_3f₀ phase (deg) · open=0, -170 deg

Using Cowork or Claude.ai, benchmark the three models. Experiment with 5 seeds. For each seed, optimize the circuit design using built-in A* and then NM.

For each seed, record metrics from the cascaded optimizers:

Compare Closed-Form vs. margin-first build vs. comprehensive model.

-Tabulate Gain, Pout, PAE, OP1dB, S₁₁ (5 metrics × 10 seeds = 40 cells).

-Identify which metric the closed-form most over- or under-estimates.

Cross-check both thermal designs: compute junction temperature rise ΔT_j at peak Pout. Which design runs cooler? By how many °C?

-Build a 2×2 comparison table: rows = {Performance-first, Margin-first}, columns = {Fitness, min-spec-margin (dB), ΔT_j (°C), PAE @ 6dB back-off}.

Visualize all of your data

Supplemental

Margin vs. Performance builds

design choices

2026年5月8日星期五

Training Pipeline in Claude Cowork- OPC lithography hotspot detection code

wrap in slides

2026年5月5日星期二

HW#9 RF PA Driver Design (Comparing optimization algorithms and pipelines)

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#9 [your id, your name]

只要做第一題

1. Benchmark the three algorithms (GD, NM, A*) and their cascades (one designed by you and the other design by AI )

For the five methods, each runs with 10 seeds
Tabulate Gain, Pout, PAE, OP1dB, S₁₁ (5 methods = 5 tables, each table with 5 metrics × 10 seeds = 40 cells).
Visualize all of your data

Two-stage Cascode Class-AB RF PA Driver targeting 5G n78 (3.5 GHz) in TSMC 28nm RF

Build Sub 6 GHz Power Amplifier Optimizer with Die Synced

share, artifact (Closed-Form)

Benchmark using Claude, Benchmark results

2026年4月28日星期二

HW#8 Claude Cowork

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#8 [your id, your name]

Part 1

Use Claude CoWork to benchmark BJT Differential Pair

1. Experiments with 30 seeds

schematic with parameter optimizer

2. The SA code is flawed. Therefore Ad, CMRR, PM cannot be optimized. Use Cowork to diagnose and fix the code. Rerun the bencmark.

Hint: prompts for CoWork

Prompts for Claude Chat

Part 2

Benchmark the P&R for OP 741.

Experiment with 3 seeds

Measure success, congestions, wirelength, overlap pairs (before/after), Vin length match

Placer & Router for OP 741

benchmark

2026年4月27日星期一

AI Tool Decision

cowork vs. chat, projector friendly

py & bash execution tool use & container, projector friendly

cowork vs openclaw, projector friendly

2026年4月19日星期日

SWERV RISC IC Design

baseline macro 32, metal layers 3, die 550 × 600 μm

add timing

add CTS

add std cells

add logistic prob of wins

why disable QPO

best seed

no QPO

10 seeds with QPO

No QPO vs. QPO with 10 seeds

Criterion to turn off (share),

QPO Decision Boundary

Bit sliced macro 28, metal layers 9, die 690 × 750 μm

2026年4月17日星期五

Optimize PCB trace routing for the Differential Pair Circuit on PCB

Components on PCB

imperfect design

schematic fix

Make it layer-aware with two layers

Add Pathfinder

eliminate phantom

trace routing, share, share 2, share 3

2026年4月14日星期二

Common issues in BJT diff pair design

BJT diff pair

Routing

(by TA)

1. unfinished routing

2. one stage diff pair 是沒有 miller 電容 cc

miller 電容在 stage 2

Parameter Optimization

(by TA)

1. SA 是無效的

檢查sa 效能

2. 檢查是否合規

gain 47.6 db 不夠

PM 0 很危險，不穩定

GBW 太大

設計目標 (3.3V):
Ad ≥ 50 dB  |  CMRR ≥ 80 dB
GBW ≥ 100 MHz  |  PM 55°–75°
Vos ≤ 1 mV  |  Pd ≤ 20 mW
Poly R: 250 Ω/sq (±20%)
MIM C: 1 fF/μm² (±15%)


refer to sample

2026年4月13日星期一

HW#7 Analog IC Design

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#6 [your id, your name]

任選1題

1 (a) A BJT Differential Pair IC Die (share) is incorrectly designed. Fix the die.

(b) Make a schematic

(d) Placement & Routing for the die

For example you may use Quadratic Placement & ILP+PathFinder+A* Routing

2. Design 2-stage diff pair (share from very simple diff pair)

(a) Make a schematic,

(b) Draw a silicon die, considering Miller Compensation,

See example of P&R+opt compo

2026年4月8日星期三

健康照護科技專題(二) Syllabus 2026 Fall

(切換完整版課綱)

開場

Unit 1: AI Computer Vision

CNN (Convolutional Neural Networks) Handwashing

YOLO (You Only Look Once) YOLOv7 list

ViT (Vision Transformers) wafer defects heat map comparison

VLM (Vision Language Models) nutrition analysis

Tesla AI Vision

HW#1 AI in Computer Vision

Unit 2: 盲人環境輔助理解，空間導航

真實世界 3d 模型製作

3d 導航(why 3D)

HW#2 Understanding environments

Unit 3: 3d障礙偵測演算法

3d障礙全域分析

Simulating A Navigation Assistant with sonar

HW#3 Obstacle detection

Unit 4: 避障演算法

Voronoi

Voronoi 2D navigation (show Voronoi) (Rural Road 2d)

Voronoi-based Safe Routing Planning (Country Alley 2d)

Voronoi waypoints for navigation (share) (Campus Alley 3d) vs. non Voronoi

3D Voronoi障礙偵測 with A*

A* search for Voronoi Navigation around moving obstacles

Unit 5: 環境安全檢測與評估視覺化 using Claude

Hazard detection (環境危害偵測)

意外事件預測與模擬

Home Hazard chain identification and animation （居家危害鏈偵測與危害視覺化）

Unit 6:

Unit 7: AI for Game Designing

Games

Unit 8 Space-Time Evolution

Geological evolution of Taiwan

Unit 9 Advanced Prompts

How to scale up: Compound Artifacts

如何合成複雜創作

Unit 10

AI for Academic Documentation

__________________________________________________________________

規模 9.0 程式設計的地震

Anthropology

Human migration

Design

Biology

Cat coat colors: 貓的花色遺傳模擬
生物呼吸中的量子效應互動模擬

6/2 AI for naturalistic modeling

Fractals

6/9 Prompts for Accuracy and High Achievement (I)

Advanced Prompts

6/16 Prompts for Accuracy and High Achievement (II)

Engineering

___________________________________________________________

Prompt Engineering Guide

Japan in Geological evolution

Document Editing Prompt

Prompts for scientific accuracy

Scientific animation
Financial Analysis in AI

2026年4月7日星期二

HW#6 A* Circuit Optimization

本次作業詳細說明

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#6 ［your id, your name]

任選一題

1. Design a Two-Stage BJT Amplifier according to goals specified using A* (Parameters to optimize RE1, RC1. RE2. RC2)

A* search for optimization, share (c_mu=3 pF, c_pi=22 pF)

2. Optimize LM3886 class AB audio amplifier IC using A* (Parameters to optimize: resistors except the load)

LM3886

A Search Setup*

State space: 5 components × 5 E12 values each = 3,125 possible states
g(n): actual steps taken from the start configuration
h(n): circuit performance cost (the heuristic) — sum of 5 weighted penalties
f(n) = g + h: A* priority queue ordering

Cost function (5 components, all minimized):

Gain: quadratic penalty for deviation from 26 dB (20×)
f_low: penalty if low-frequency cutoff exceeds 10 Hz
f_high: penalty if high-frequency cutoff falls below 100 kHz
Bias: penalizes Rb1 ≠ Rb2 (asymmetric thermal tracking)
Re stability: log-scale penalty away from 0.47 Ω optimum

Weight/ Forms

Are Re1 and Re2 Always Equal?

the architecture inside the LM3886 and TDA7293

optimizer A* (share)

Lessons learned from AI use

Lesson 1

Design a Two-Stage BJT Amplifier (Parameters to optimizeRE1, RC1. RE2. RC2)

Note this is a degenerate model

A* search for optimization, share 4-parameter (for bypassed model c_mu=3 pF, c_pi=22 pF) note: goal reached is actually current step, not current best