cowork vs. chat, projector friendly
py & bash execution tool use & container, projector friendly
2026年4月27日 星期一
2026年4月19日 星期日
SweRV RISC IC Design: Macro Routing from Baseline to Bit-Sliced Buses
This post follows one routing demo through six versions. The design is swerv_wrapper, a simplified model of the SRAM macros around the open-source SweRV EH1 RISC-V core [1]. Every version runs the same browser-based 3D router, A* search [2] inside PathFinder's negotiated-congestion loop [3], and each one adds a single feature: timing, a clock tree, standard-cell density, a rule that picks the macro placer, and finally bit-sliced buses.
- Baseline. All 45 nets route on three metal layers in 3 iterations. The run stops by phantom-exit: the 4 cells still shared at the end are shared by nets with a common endpoint.
- Timing. With 1.5 ps per grid step, 3 ps per via and a 2.5 GHz clock, the worst slack (WNS) is +94 ps, so no path fails.
- Clock tree. A 15-segment tree in place of eight separate clock wires cuts the routed clock skew from 87.0 ps to 54.0 ps and the total wirelength from 1260 λ to 1166 λ.
- Standard cells. A density penalty at 50% costs 6 ps of WNS (+92 to +86 ps) and 12 ps of skew (54.0 to 66.0 ps).
- Placer choice. A logistic rule gives the force-directed placer (QPO) a 22.6% chance of beating the hand-made floorplan, so the page offers simulated annealing instead.
- Bit-slicing. Splitting buses into one-bit wires turns 45 nets into 387 wires; partway through the first iteration on eight layers, 475 cells are already overused, and 40 iterations do not clear them.
- Scope. A teaching model: hand-written netlist, one fixed floorplan, one run per stage, and λ is one grid step. See Limits.
The design · The router · 1 Baseline · 2 Timing · 3 Clock tree · 4 Std cells · 5 QPO or SA · 6 Bit-slicing · Numbers · Reading the HUD · Limits · Sources
Updated 3 November 2026. The original post of 19 April 2026 is kept at its own address. The interactive pages it linked to are no longer online. Rebuilt copies of every stage, with English labels, are collected at SweRV routing demos.
1. The design
swerv_wrapper is a cartoon of the real core. Its 32 SRAM macros share one 8 × 4-cell footprint whatever their capacity, the nets are written by hand, and standard cells appear only as a density estimate (stage 4). The macros sit in seven rows, five per row and two in the last, inside a ring of 34 pads (24 signal and clock pads, 10 VDD/VSS pads) and VDD/VSS power rings. The page gives the die as 550 × 600 μm in the ASAP7 7 nm predictive process [4].
| Macro | Count | Size | Role in the core |
|---|---|---|---|
| icache | 9 | 32 Kbit | L1 instruction cache |
| dccm | 4 | 64 Kbit | data closely coupled memory |
| btb | 4 | 4 Kbit | branch target buffer |
| bht | 4 | 2 Kbit | branch history table |
| ras | 2 | 8 entries | return address stack |
| iccm | 4 | 64 Kbit | instruction closely coupled memory |
| tlb | 3 | 32 entries | address translation |
| tag | 2 | 8 Kbit | cache tags |
| Total | 32 |
Table 1. Macros, with the sizes listed in the page's macro inventory.
| Net group | Nets | Widths | From → to |
|---|---|---|---|
| AXI write | 5 | wdata 32 b ×3, wstrb 4 b, wvalid | top pads → dccm_0–3 |
| AXI read | 4 | rdata 32 b ×3, rresp 2 b | icache_4, icache_8, dccm_0, btb_1 → right pads |
| AXI address | 5 | araddr 32 b ×2, awaddr 32 b, arvalid, awvalid | bottom pads → icache_5–7, dccm_1, dccm_3 |
| Clock | 8 | clk | clk pad (left) → 8 macros |
| Reset | 6 | rst_n | rst_n pad (left) → 6 macros |
| Branch prediction | 7 | btb_target 32 b ×4, btb_way 32 b, ras_addr 32 b, bht_counter 2 b | btb_n → bht_n, btb_2 → btb_3, ras_0 → ras_1, bht_0 → ras_0 |
| ICCM chain | 3 | iccm_data 128 b ×3 | iccm_0 → iccm_1 → iccm_2 → iccm_3 |
| TLB and tag | 4 | tlb_ppn 32 b ×3, tag_valid 32 b | tlb_0, tlb_1 → tag_0; tlb_2 → tag_1; tag_0 → tag_1 |
| Test | 3 | test_en, scan_en, jtag | left pads → iccm_0, tlb_0, tag_0 |
| Total | 45 |
Table 2. The 45 nets. Unmarked widths are 1 bit. Until stage 6 each bus is routed as a single net.
The routing grid has 80 × 60 cells on each metal layer, and a cell holds one wire per layer. Wirelength is counted in grid steps, written λ. Stages 1–5 route on M1–M3 with power straps on M4; stage 6 routes on M1–M8 with power straps on M9.
2. The router
All six versions share one router. Nets are routed one at a time with A* search on a three-dimensional grid: four moves within a layer, plus a via up or down. Layers alternate their preferred direction (M1 horizontal, M2 vertical, and so on). A net may start and end at any free cell along its macro's or pad's boundary, on any layer, so a macro offers up to 28 pin cells, fewer where a pad is in the way.
PathFinder then negotiates. Every iteration rips up and reroutes all nets, and a cell gets more expensive with its present overuse and with its history of overuse, so nets that can detour cheaply leave the contested cells to nets that cannot [3]. The cost of entering a cell, as the page computes it:
c = base + cong · (1 − 0.6 k) + 3 · density · PLACE_DENSITY
cong = (1 + p) · pres_fac + h · hist_fac
base is 1 for a step in the layer's preferred direction, 1.5 for a step against it and 1 for a via. p is the number of nets already in the cell in this iteration (the first term of cong is dropped when p = 0), and h is the cell's history: after each iteration an overused cell's history grows by 1.5 times its occupancy, and every other cell's history decays by a factor of 0.8. pres_fac starts at 0.5 and is multiplied by 2.6 each iteration, up to 80; hist_fac starts at 1 and grows by 1.2 each iteration, up to 30. The timing criticality k arrives in stage 2 and the density term in stage 4, so the baseline cost is base + cong.
Net order. Before the first iteration the nets are sorted by 60 × priority + max(0, 50 − d), where priority is a hand-set value from 0 (test signals) to 3 (clock) and d is the Manhattan distance between the endpoints. The HUD calls this list “ILP 排序 (critical first)”, but it is a sort, not an integer linear program. After each iteration the nets are re-sorted, most congested first.
Phantom-exit. A run stops after 40 iterations, or earlier once every net is routed and no real congestion is left. A cell is overused when two or more nets occupy it on the same layer. If the nets in an overused cell share an endpoint macro or pad, the router calls the overlap phantom; otherwise it is real (Fig. 1). When only phantom overlaps remain, the run ends with the label phantom-exit. Sharing is harmless when the nets are branches of one signal, such as the clock wires leaving the clk pad, but the same test also forgives two different signals that enter one macro through the same cell, which a real chip cannot do.
Fig. 1. How the router classes an overused cell (outlined). Solid outline: real, routing continues. Dashed outline: phantom, allowed at exit.
3. Stage 1: baseline
Fig. 2. Stage 1, baseline: 32 macros, three routing layers, 550 × 600 μm. White blocks are SRAM macros, squares on the die edge are pads and gold posts are vias. HUD: done (phantom-exit) after 3 of 40 iterations, 45/45 nets, 4 overused cells, all phantom.
The baseline routes the 45 nets on M1–M3 with cost base + cong. PathFinder needs three iterations; the 4 cells still shared at the end are all phantom, so the run ends by phantom-exit. Total wirelength is 1268 λ with 39 vias. There is no delay model yet, so the clock skew is the spread of the eight clock wires' lengths: 57 λ.
Try it in the rebuilt demos: stage 1, recreated from the stage 2 page with timing switched off.
4. Stage 2: add timing
Fig. 3. Stage 2, timing added. The PathFinder panel now shows WNS +94 ps and TNS 0 ps; done by phantom-exit after 4 iterations. Routes turn redder as their nets become timing-critical.
Stage 2 runs static timing analysis after every iteration. Each signal net is timed as a register-to-register path: it launches 150 ps after the clock edge (the SRAM's clock-to-Q time), spends its wire delay, and must arrive 50 ps (the setup time) before the next edge of a 400 ps clock, which is 2.5 GHz. Wire delay is 1.5 ps per grid step plus 3 ps per via, so
slack = 400 − 50 − 150 − delay = 200 ps − delay
WNS is the smallest slack and TNS the sum of the negative ones. The nets are then ranked by slack, and each gets a criticality k from 0 (most slack) to 1 (least); clock nets get a fixed 0.7. In the next iteration a net's congestion penalty is multiplied by 1 − 0.6 k, so the most critical net pays only 40% of it and can cut through contested cells while others detour.
Result: four iterations, WNS +94 ps and TNS 0, so the slowest signal net has 106 ps of wire delay. Total wirelength is 1260 λ with 33 vias. Clock skew is now in picoseconds: the eight routed clock wires differ by 87.0 ps, close to the 57 λ × 1.5 ps ≈ 86 ps of stage 1. Criticality scales only the congestion penalty, so it changes a route only where the route meets congestion, and this sparse design has little.
Try it in the rebuilt demos: stage 2, timing-driven routing.
5. Stage 3: add a clock tree (CTS)
Fig. 4. Stage 3, clock tree added: 52/52 nets, clock skew 54.0 ps (the page's star estimate is 90.0 ps), WNS +92 ps. The routing order now starts with the tree segments.
Up to stage 2 the clock is a star: eight separate wires from the clk pad, one per clocked macro. Stage 3 builds a tree instead, in the spirit of the method of means and medians [5]. A trunk runs from the clk pad to the centroid of the eight clocked macros. There the macros are split in half along the wider of their x and y spreads, and a trunk runs to the centroid of each half (moved to the nearest free cell). After one more split, each of four branch points feeds its two macros directly. That makes 7 trunk segments and 8 leaf segments. These 15 segments replace the 8 star wires, so the router now has 52 nets, and the segments are routed first.
Skew is measured on the routed tree as the spread of the summed segment delays from the clk pad to each macro: 54.0 ps, against 87.0 ps for the routed star of stage 2. The “star: 90.0 ps” in the HUD is the page's estimate from Manhattan distances before routing. Because the trunks are shared, total wirelength drops from 1260 λ to 1166 λ. WNS is +92 ps after six iterations.
The page's flow panel calls this an H-tree, but it is a geometric bisection with no buffers and no delay balancing. A production clock tree inserts buffers and tunes wire lengths so that every leaf sees the same delay.
Try it in the rebuilt demos: stage 3, clock tree.
6. Stage 4: add standard cells
Fig. 5. Stage 4, standard-cell density with PLACE_DENSITY = 50% (slider in the toolbar): WNS +86 ps, clock skew 66.0 ps, still phantom-exit after 6 iterations.
On a real die the space between macros is filled with standard cells (about 108 K gates, by a comment in the page's code), and their pins compete with the router for tracks. Stage 4 models that demand without placing any cells. Every net other than the clock tree spreads a weight of log₂(width + 1) + 1 over its bounding box, one cell wider on each side; the map is blurred over 3 × 3 cells and scaled to 0–1. A* then adds 3 × density × PLACE_DENSITY to every step and via, on every layer.
At PLACE_DENSITY = 50% the run still ends by phantom-exit after six iterations, but WNS drops by 6 ps to +86 ps and clock skew rises by 12 ps to 66.0 ps, as nets detour around the dense regions (total wirelength +27 λ, to 1193 λ).
Try it in the rebuilt demos: stage 4, standard-cell density.
7. Stage 5: QPO or simulated annealing
Every run so far keeps the hand-made rows of macros. The page also has a placer, QPO, a force-directed relative of quadratic placement such as GORDIAN [6]. Each macro moves toward the weighted centroid of the macros and pads it connects to, against a repulsion term and an overlap penalty, for 80 iterations; two rounds of refinement against a quick congestion estimate follow.
Should QPO replace the rows? Up to stage 4 a fixed rule decided. Fill below 20% with a footprint below 0.08 of the grid width meant useful; fill above 40%, or a footprint of 0.10 or more, meant harmful; anything else was marginal. SweRV's macros cover 21.3% of the grid and are 0.10 of its width, so in Figs. 2–5 the toolbar shows “QPO 有害” (QPO harmful) and the QPO button is greyed out.
Stage 5 replaces the rule with a logistic estimate of the probability that QPO beats the existing placement:
P(QPO wins) = σ(4.0 − 25.0 · fill − 0.3 · log₂N + 1.5 · fill · log₂N)
With N = 32 macros and fill = 0.213 this gives 22.6%. At 50% or more the page keeps QPO, between 30% and 50% it warns, and below 30% the placement button becomes “SA 退火”: simulated annealing [7] on half-perimeter wirelength weighted by priority. The annealer makes 5000 moves (60% shifts of up to 3 columns and 2 rows, 40% swaps of two macros), rejects any move that makes macros overlap, and cools from temperature 50 by a factor of 0.995 per move. This stage has no screenshot of its own; its verdict appears in the toolbar and console of Fig. 6.
A code comment says the coefficients were fitted on a 12-design sweep, but the sweep is not published and the coefficients are round numbers. Read the 22.6% as a rule of thumb, not as a calibrated probability.
In the rebuilt page, annealing lowers the placement cost from 1046 to 785, but the routing that follows leaves test_en → iccm_0 unrouted in every iteration and stops at the 40-iteration limit with 51 of 52 nets. Once a placer has run, the page's obstacle map also blocks an 8 × 4 area, the size of a macro, around each pad, and the annealer moves tlb_0 next to the left pad ring. Together they close the test_en pad's pin cells into a pocket that no path can leave.
Try it in the rebuilt demos: stage 5, QPO or simulated annealing.
8. Stage 6: bit-sliced buses
Fig. 6. Stage 6, bit-sliced buses on eight routing layers, partway through iteration 1: 312/387 wires routed, 475 overused cells. Toolbar: “SA 退火” and “QPO OFF (22.6%)”. Console: the logistic verdict and “Bit-slice: 45 nets → 380 (25 buses expanded, cap=16)”. The chat panel on the left of the original screenshot is cropped out.
Until stage 5 a 32-bit bus is routed as a single net. Stage 6 splits every bus into one-bit wires and gives each wire a single pin cell at each end, sampled evenly from the macro's pin cells across the direction of the bus. Buses are capped at 16 wires (BIT_SLICE_CAP = 16), so every 32-bit and 128-bit bus becomes 16 wires, and the 2- and 4-bit buses keep one wire per bit. The 45 nets become 380 wires from 25 expanded buses, and with the 15 clock-tree segments in place of the 8 clock wires the router faces 387. The stack grows to eight routing layers, M1–M8 with alternating directions, plus power straps on M9.
Fig. 6 catches the first iteration in progress: 312 of 387 wires routed, 7718 λ of wire and 162 vias so far, and 475 overused cells, against 4–6 at the end of stages 1–4. In the first iteration pres_fac is still 0.5, so nets barely avoid each other; that overlap is what the later iterations must negotiate away. With more than seven times as many wires on the same 80 × 60 grid, this is the stage where the design stops being sparse.
The rebuilt page shows how that ends. Eighteen wires have their only pin cell in a pocket between two pads under bht_2 or bht_3, at the bottom edge of the die, so they can never route: a whole bus could use any free cell along the macro, but a one-bit wire gets a single cell, chosen without checking that it can be reached. The overlaps do not clear either. After the full 40 iterations 369 of 387 wires are routed, 811 cells are overused (621 of them real) and WNS is −346 ps, as wires detour around one another.
The original caption for this stage, “macro 28, metal layers 9, die 690 × 750 μm”, partly describes the last version of the page rather than the screenshot. Both have nine metal layers, eight for routing and one for power, but the screenshot still has 32 macros on 550 × 600 μm. The last version drops four macros (bht_2, bht_3, tlb_2, tag_1), keeps 38 nets and uses a 100 × 75 grid. Its fill falls to 11.9%, and the same logistic rule then gives about 61%, so QPO stays on. Its 38 nets become 318 wires, and every one of them routes in the first iteration; after 40 iterations 18 cells are still overused, 7 of them real. QPO cuts the first iteration's clock skew from 69.0 ps to 21.0 ps, but 7 wires then have their only pin cell boxed in at the die edge, for the same pad reason as in stage 5.
Try it in the rebuilt demos: stage 6, bit-sliced buses, and the last April version.
9. The numbers side by side
| 1 Baseline | 2 Timing | 3 Clock tree | 4 Std cells | 6 Bit-sliced * | |
|---|---|---|---|---|---|
| Routing layers | M1–M3 | M1–M3 | M1–M3 | M1–M3 | M1–M8 |
| Nets routed / total | 45 / 45 | 45 / 45 | 52 / 52 | 52 / 52 | 312 / 387 |
| Iterations | 3 | 4 | 6 | 6 | 1, running |
| Overused cells | 4 | 4 | 6 | 4 | 475 |
| WNS | — | +94 ps | +92 ps | +86 ps | — |
| TNS | — | 0 ps | 0 ps | 0 ps | — |
| Clock skew | 57 λ | 87.0 ps | 54.0 ps | 66.0 ps | 61.5 ps |
| Total wirelength | 1268 λ | 1260 λ | 1166 λ | 1193 λ | 7718 λ |
| Vias | 39 | 33 | 40 | 39 | 162 |
Table 3. Read from the HUDs in Figs. 2–6, one run per stage; the rebuilt demo pages give the same numbers. Stages 1–4 end by phantom-exit, and all their overused cells are phantom. Stage 5 changes only the placer choice and has no screenshot. * Stage 6 is partway through iteration 1, so its numbers are partial.
Across the finished stages, the clock tree is the step that pays most: it removes 94 λ of wire and cuts skew by more than a third. Timing barely changes the routes on a design with this much slack, density costs a few picoseconds, and bit-slicing multiplies the routing problem by more than seven.
10. Reading the HUD
The screenshots keep the page's Chinese labels; the rebuilt demos use English ones. In English:
| HUD label | Meaning |
|---|---|
| 階段 | phase: ILP排序 or CTS+ILP排序 (ordering), Iter n (iteration n), 完成 (done) |
| 迭代 | PathFinder iteration, n of 40 |
| pres_fac · hist_fac | present and history congestion factors |
| 壅塞節點 | overused cells, phantom ones included |
| WNS · TNS | worst slack · total negative slack |
| A* 狀態 · 當前網絡 | A* status · the net being routed |
| Open · Closed | sizes of the A* open list and closed set |
| f=g+h | cost so far plus estimate, for the node being expanded |
| ILP 排序 (critical first) | routing order, highest priority first |
| 布線統計 · 完成 | routing statistics · nets routed / total |
| Clock skew | spread of clock arrival, in λ before stage 2 and in ps after |
| Total WL · Vias | wirelength in grid steps · layer changes |
| 第n輪 | iteration n (status bar) |
| P&R完成！n輪 · m/m條路由 | P&R finished after n iterations, m of m nets routed |
| 壅塞:n(全phantom) | n overused cells, all phantom |
| QPO 佈局 · QPO 有害 · 邊界 | run the QPO placer · QPO judged harmful · marginal |
| SA 退火 | run the simulated-annealing placer |
| 重置 | undo the placement |
| 開始布線 · 暫停 · 重置布線 · 速度 | start routing · pause · clear the routes · animation speed |
| Flow | show the panel that lists the flow steps |
Table 4. HUD, toolbar and status-bar labels in Figs. 2–6.
11. Limits
- A cartoon of SweRV. One footprint for every SRAM, a hand-written netlist of 45 nets, and no placed standard cells; the real core has thousands of nets.
- Nominal process. The die size and the ASAP7 label appear only in the page's titles. The model works in grid steps, and its delays are round numbers, not ASAP7 data.
- Coarse grid. 80 × 60 cells, one wire per cell per layer, and pins on any free boundary cell of a macro, on any layer.
- Simple timing. Delay is linear in length (the code calls it Elmore-simplified), with no gate delay and no buffers. Slack ignores clock arrival times, so clock skew never enters WNS.
- Phantom is a proxy. Overlaps are forgiven by shared endpoint macro or pad, not by shared signal (Fig. 1).
- Labels. “ILP” is a priority sort, the “H-tree” is an unbuffered bisection tree, and the logistic coefficients come without their data.
- One run each. Every number comes from a single run on one fixed floorplan, with no seeds averaged, and Fig. 6 is mid-run.
12. Sources
- VeeR EH1 RISC-V core (formerly SweRV EH1), CHIPS Alliance, originally from Western Digital. github.com/chipsalliance/Cores-VeeR-EH1
- P. E. Hart, N. J. Nilsson and B. Raphael, “A formal basis for the heuristic determination of minimum cost paths,” IEEE Trans. Systems Science and Cybernetics, vol. 4, no. 2, pp. 100–107, 1968. doi:10.1109/TSSC.1968.300136
- L. McMurchie and C. Ebeling, “PathFinder: A negotiation-based performance-driven router for FPGAs,” Proc. FPGA '95, pp. 111–117, 1995. doi:10.1145/201310.201328
- L. T. Clark et al., “ASAP7: A 7-nm finFET predictive process design kit,” Microelectronics Journal, vol. 53, pp. 105–115, 2016. doi:10.1016/j.mejo.2016.04.006
- M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock routing for high-performance ICs,” Proc. DAC '90, pp. 573–579, 1990. doi:10.1145/123186.123406
- J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, “GORDIAN: VLSI placement by quadratic programming and slicing optimization,” IEEE Trans. CAD, vol. 10, no. 3, pp. 356–365, 1991. doi:10.1109/43.67789
- S. Kirkpatrick, C. D. Gelatt and M. P. Vecchi, “Optimization by simulated annealing,” Science, vol. 220, no. 4598, pp. 671–680, 1983. doi:10.1126/science.220.4598.671
See also: Modern Global Placement: ePlace vs. RePlAce, on how analytic placers spread standard cells before routing.
SWERV RISC IC Design (original)
This is the original version of this post, first published on 19 April 2026 and kept unchanged below. The current version is SweRV RISC IC Design: Macro Routing from Baseline to Bit-Sliced Buses. The interactive pages linked below are no longer online. Rebuilt copies of every stage, with English labels, are collected at SweRV routing demos.
baseline macro 32, metal layers 3, die 550 × 600 μm
Bit sliced macro 28, metal layers 9, die 690 × 750 μm
2026年4月17日 星期五
Optimize PCB trace routing for the Differential Pair Circuit on PCB
Make it layer-aware with two layers
eliminate phantom
2026年4月14日 星期二
Common issues in BJT diff pair design
(by TA)
1. unfinished routing
2. one stage diff pair 是沒有 miller 電容 cc
(by TA)
1. SA 是無效的
2. 檢查是否合規
gain 47.6 db 不夠
PM 0 很危險，不穩定
GBW 太大
設計目標 (3.3V):
Ad ≥ 50 dB | CMRR ≥ 80 dB
GBW ≥ 100 MHz | PM 55°–75°
Vos ≤ 1 mV | Pd ≤ 20 mW
Poly R: 250 Ω/sq (±20%)
MIM C: 1 fF/μm² (±15%)
refer to sample
2026年4月13日 星期一
HW#7 Analog IC Design
課堂練習
Deadline: This Saturday at 23:59
Send all the share links to me chang212@gmail.com by email with subject HW#6 [your id, your name]
任選1題
1 (a) A BJT Differential Pair IC Die (share) is incorrectly designed. Fix the die.
(b) Make a schematic
(c) Do parameter optimization via SA (simulated annealing)
(d) Placement & Routing for the die
For example you may use Quadratic Placement & ILP+PathFinder+A* Routing
(a) Make a schematic,
(b) Draw a silicon die, considering Miller Compensation,
(c) Do P&R (Placement & Routing) for the IC
See example of P&R+opt compo
2026年4月8日 星期三
健康照護科技專題(二)
這些主題都以 AI 輔助、不需自行撰寫底層程式
本課程限定使用 Claude AI，有特殊原因必須使用其他ＡＩ者需在選課前與老師商量。
Unit 1: AI Computer Vision, 1 week
CNN (Convolutional Neural Networks) Handwashing
YOLO (You Only Look Once) YOLOv7 list
ViT (Vision Transformers) wafer defects heat map comparison
VLM (Vision Language Models) nutrition analysis
HW#1 AI in Computer Vision
Simulating A Navigation Assistant with sonar
Voronoi
Voronoi 2D navigation (show Voronoi) (Rural Road 2d)
Voronoi-based Safe Routing Planning (Country Alley 2d)
Voronoi waypoints for navigation (share) (Campus Alley 3d) vs. non Voronoi
3D Voronoi障礙偵測 with A*
A* search for Voronoi Navigation around moving obstacles
Unit 5: 環境安全檢測與評估視覺化, 1 week
Hazard detection (環境危害偵測)
Home Hazard chain identification and animation （居家危害鏈偵測與危害視覺化）
Unit 6: World Model for Artificial General Intelligence (AGI), 3 weeks
Unit 7: AI for Game Designing, 2 weeks
- 體感洗手練習遊戲
- AI打地鼠遊戲
- 跳舞評分機
- 訊息處理，心智障礙生活輔助 (games for health)
Unit 8: Space-Time Evolution, 2 weeks
Unit 9: Advanced Prompts, 1 week
Unit 10: Machine Learning for Asset Management, 2 weeks
__________________________________________________________________
本專題課程以 AI 輔助探討健康照護科技之應用，涵蓋 AI 電腦視覺、盲人環境輔助理解與空間導航、3D 障礙偵測與避障演算法（Voronoi、A*）、環境安全與居家危害偵測視覺化、World Model (AGI)、健康促進遊戲設計、以及 AI 學術論文寫作等主題，從實作中培養運用 AI 解決健康照護相關問題的能力。
backup
Anthropology
Design
訂閱：
文章 (Atom)