健康照護科技專題 : 2026

2026年4月28日星期二

HW#8 Claude Cowork

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#8 [your id, your name]

Part 1

Use Claude CoWork to benchmark BJT Differential Pair

1. Experiments with 30 seeds

schematic with parameter optimizer

2. The SA code is flawed. Therefore Ad, CMRR, PM cannot be optimized. Use Cowork to diagnose and fix the code. Rerun the bencmark.

Hint: prompts for CoWork

Prompts for Claude Chat

Part 2

Benchmark the P&R for OP 741.

Experiment with 3 seeds

Measure success, congestions, wirelength, overlap pairs (before/after), Vin length match

Placer & Router for OP 741

benchmark

2026年4月27日星期一

AI Tool Decision

cowork vs. chat, projector friendly

py & bash execution tool use & container, projector friendly

cowork vs openclaw, projector friendly

2026年4月19日星期日

SWERV RISC IC Design

baseline macro 32, metal layers 3, die 550 × 600 μm

add timing

add CTS

add std cells

add logistic prob of wins

why disable QPO

best seed

no QPO

10 seeds with QPO

No QPO vs. QPO with 10 seeds

Criterion to turn off (share),

QPO Decision Boundary

Bit slided macro 28, metal layers 9, die 690 × 750 μm

2026年4月17日星期五

Optimize PCB trace routing for the Differential Pair Circuit on PCB

Components on PCB

imperfect design

schematic fix

Make it layer-aware with two layers

Add Pathfinder

eliminate phantom

trace routing, share, share 2, share 3

2026年4月14日星期二

Common issues in BJT diff pair design

BJT diff pair

Routing

(by TA)

1. unfinished routing

2. one stage diff pair 是沒有 miller 電容 cc

miller 電容在 stage 2

Parameter Optimization

(by TA)

1. SA 是無效的

檢查sa 效能

2. 檢查是否合規

gain 47.6 db 不夠

PM 0 很危險，不穩定

GBW 太大

設計目標 (3.3V):
Ad ≥ 50 dB  |  CMRR ≥ 80 dB
GBW ≥ 100 MHz  |  PM 55°–75°
Vos ≤ 1 mV  |  Pd ≤ 20 mW
Poly R: 250 Ω/sq (±20%)
MIM C: 1 fF/μm² (±15%)


refer to sample

2026年4月13日星期一

HW#7 Analog IC Design

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#6 [your id, your name]

任選1題

1 (a) A BJT Differential Pair IC Die (share) is incorrectly designed. Fix the die.

(b) Make a schematic

(d) Placement & Routing for the die

For example you may use Quadratic Placement & ILP+PathFinder+A* Routing

2. Design 2-stage diff pair (share from very simple diff pair)

(a) Make a schematic,

(b) Draw a silicon die, considering Miller Compensation,

2026年4月8日星期三

健康照護科技專題(二) Syllabus 2026 Fall

(切換完整版課綱)

開場

Unit 1: AI Computer Vision

CNN (Convolutional Neural Networks) Handwashing

YOLO (You Only Look Once) YOLOv7 list

ViT (Vision Transformers) wafer defects heat map comparison

VLM (Vision Language Models) nutrition analysis

Tesla AI Vision

HW#1 AI in Computer Vision

Unit 2: 盲人環境輔助理解，空間導航

真實世界 3d 模型製作

3d 導航(why 3D)

HW#2 Understanding environments

Unit 3: 3d障礙偵測演算法

3d障礙全域分析

Simulating A Navigation Assistant with sonar

HW#3 Obstacle detection

Unit 4: 避障演算法

Voronoi

Voronoi 2D navigation (show Voronoi) (Rural Road 2d)

Voronoi-based Safe Routing Planning (Country Alley 2d)

Voronoi waypoints for navigation (share) (Campus Alley 3d) vs. non Voronoi

3D Voronoi障礙偵測 with A*

A* search for Voronoi Navigation around moving obstacles

Unit 5: 環境安全檢測與評估視覺化 using Claude

Hazard detection (環境危害偵測)

意外事件預測與模擬

Home Hazard chain identification and animation （居家危害鏈偵測與危害視覺化）

Unit 6:

Unit 7: AI for Game Designing

Games

Unit 8 Space-Time Evolution

Geological evolution of Taiwan

Unit 9 Advanced Prompts

How to scale up: Compound Artifacts

如何合成複雜創作

Unit 10

AI for Academic Documentation

__________________________________________________________________

規模 9.0 程式設計的地震

Anthropology

Human migration

Design

Biology

Cat coat colors: 貓的花色遺傳模擬
生物呼吸中的量子效應互動模擬

6/2 AI for naturalistic modeling

Fractals

6/9 Prompts for Accuracy and High Achievement (I)

Advanced Prompts

6/16 Prompts for Accuracy and High Achievement (II)

Engineering

___________________________________________________________

Prompt Engineering Guide

Japan in Geological evolution

Document Editing Prompt

Prompts for scientific accuracy

Scientific animation
Financial Analysis in AI

2026年4月7日星期二

HW#6 A* Circuit Optimization

本次作業詳細說明

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#6 ［your id, your name]

任選一題

1. Design a Two-Stage BJT Amplifier according to goals specified using A* (Parameters to optimize RE1, RC1. RE2. RC2)

A* search for optimization, share (c_mu=3 pF, c_pi=22 pF)

2. Optimize LM3886 class AB audio amplifier IC using A* (Parameters to optimize: resistors except the load)

LM3886

A Search Setup*

State space: 5 components × 5 E12 values each = 3,125 possible states
g(n): actual steps taken from the start configuration
h(n): circuit performance cost (the heuristic) — sum of 5 weighted penalties
f(n) = g + h: A* priority queue ordering

Cost function (5 components, all minimized):

Gain: quadratic penalty for deviation from 26 dB (20×)
f_low: penalty if low-frequency cutoff exceeds 10 Hz
f_high: penalty if high-frequency cutoff falls below 100 kHz
Bias: penalizes Rb1 ≠ Rb2 (asymmetric thermal tracking)
Re stability: log-scale penalty away from 0.47 Ω optimum

Weight/ Forms

Are Re1 and Re2 Always Equal?

the architecture inside the LM3886 and TDA7293

optimizer A* (share)

Lessons learned from AI use

Lesson 1

Design a Two-Stage BJT Amplifier (Parameters to optimizeRE1, RC1. RE2. RC2)

Note this is a degenerate model

A* search for optimization, share 4-parameter (for bypassed model c_mu=3 pF, c_pi=22 pF) note: goal reached is actually current step, not current best

revised to OCT model A* search for optimization, share 4-parameter (for bypassed model c_mu=3 pF, c_pi=22 pF)

using 2N2222 parameters (share)

Lesson 2

Lesson 3

(a) Degenerative/NonDegenrative ＯＣＴ Global Exhaustive Search/A*

(b) plus MNA-based Freq sweep

2026年3月31日星期二

HW#5 LNA Optimization

1, 2 任選一題

本次作業詳細說明

1. Make a GD/(A*)+MNA Optimizer on a Apple C1 LNA Die

Hint: share

2. To achieve the 15-20 dB gain target and improve the LNA performance to match the schematic specs, use Differential Evolution Optimization to optimize the LNA performance.

Must verify your results to meet spec and parameters have to be realistic.

DE+MNA Optimizer on Die

demo (transfer function), ngspice, MNA of LNA

Want to get these figures, see the Claude share. (Opus 4.6)

2026年3月24日星期二

HW#4 RF IC Design

建議工具

使用 Claude Sonnet 4.6 推理模式(手動切換，免費用戶額定時間內只能使用三次)

使用 ChatGPT 5 推理模式(自動切換)

使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)

How to publish a Claude artifact

How to share a ChatGPT link

How to share Gemini Link

Content share 作業繳交格式

share only link, pure text, markdown (md)
no attachments accepted, no html, screen dump, or png
non-compliant homework will be rejected and returned to you

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#4 [your id, your name]

Study Apple C1 Architecture

(a) On Claude, Run NGSpice for the LNA using given parameters. If the results do not match, explain why.

(b) Run an MNA simulation (Modified Nodal Analysis, as used in Cadence Spectre engine). Optimize the IC design to meet specs.

Optimized parameters (share)

running ngspice in Claude VM (amazing story)

initial parameters (MNA)

optimized parameters (share)

(c) Perform DRC (Design Rule Check) for the 3.5 GHz LNA. If it is not entirely design rule compliant, redesign to make the layout more DRC driven.

(DRC, share) (DRC-driven, artifact)

2026年3月13日星期五

Follow up of HW#3, Placement

PA Parameter Optimization

original (analytical), Hessian, MNA (post QP+SA)

PA Lessons, PA Verified by by computing the exact KCL residual at its converged solution, not because of blow up of MNA (share)

PA issues system crash, reality check, UI design

LNA reality check in simulator, prompt for spec compliance

LNA v3 (closed-form), V3 pathway to tape-out (advanced, ok omitted)

Overall

1 What is simulated annealing? shown on hyperfunctions comparing to other algorithms

2026年3月10日星期二

HW#3 Apple C1 LNA IC Design with Advanced AI

建議工具

使用 Claude Sonnet 4.6 推理模式(手動切換，免費用戶額定時間內只能使用三次)

使用 ChatGPT 5 推理模式(自動切換)

使用 Gemini 3.0 Pro 免費額度最高 1M tokens (永遠推理模式)

使用 Grok 4 推理模式(自動切換)

How to publish a Claude artifact

How to share a ChatGPT link

How to share a Grok link

How to share Gemini Link

Content share 作業繳交格式

share only link, pure text, markdown (md)
no attachments accepted, no html, screen dump, or png
non-compliant homework will be rejected and returned to you

課堂練習

Deadline: This Saturday at 23:59

Send all the share links to me chang212@gmail.com by email with subject HW#3 [your id, your name]

1. Study Apple C1 Architecture

(a) make

LNA schematic (TSMC N7 製程的完整設計流程，包含完整元件表、元件值推導公式、die 面積估算) LNA=Low Noise Amplifier

(b) make

LNA Die

prompts

LNA Optimizer (SMITH Chart, Frequency Response)

Prompts, Cont. Prompts

(d) Build a Simplified (closed-form) LNA optimizer on Die, 3.5 GHz LNA TSMC N7.

Prompts, Cont. Prompts (same as last)

(e) Build an MNA model (Modified Nodal Analysis, as used in Cadence Spectre engine) to optimize. Must verify your results to meet spec and parameters have to be realistic.